# The Semiconductor Integrated Circuits Layout-Design Act, 2000, Section 19: Registration to be prima facie evidence of validity

- Act: The Semiconductor Integrated Circuits Layout-Design Act, 2000 (Act 37 of 2000)
- In force from: 2004-05-01
- Ministry: Ministry of Commerce and Industry
- Source URL: https://indiacode.ecourtsindia.com/semiconductor-integrated-circuits-layout-design-act-2000/section/19/

## Text

(1) In all legal proceedings relating to a layout-design registered under this Act (including application under section 30), the original registration of the layout-design and all subsequent assignments and transmissions of layout-design shall be prima facie evidence of the validity thereof. (2) In all legal proceedings as aforesaid, a registered layout-design shall not be held to be invalid on the ground that it was not a registerable layout-design under section 7 except upon evidence of originality and that such evidence was not submitted to the Registrar before registration.

---
Published by eCourtsIndia together with commentary and other original matter under section 52(1)(q)(ii) of the Copyright Act, 1957.