Penalty for falsely representing a layout-design as registered
Section 57 of the Semiconductor Integrated Circuits Layout-Design Act, 2000 deals with penalty for falsely representing a layout-design as registered. No person shall make any representation with respect to a layout-design not being a registered layout-design, to the effect that it is a registered layout-design. The Act came into force on 01 May 2004.
(1) No person shall make any representation with respect to a layout-design not being a registered layout-design, to the effect that it is a registered layout-design.
(2) If any person contravenes the provisions of sub-section (1), he shall be punishable with imprisonment for a term which may extend to six months, or with fine which may extend to fifty thousand rupees, or with both.
(3) For the purposes of this section, the use in India in relation to a layout-design of the word "registered", or of any other expression referring whether expressly or impliedly to registration, shall be deemed to import a reference to registration in the register, except--
(a) where that word or other expression, is used in direct association with other words delineated in characters at least as large as those in which that word or other expression is delineated and indicating that the reference is to registration as a layout-design under the law of a country outside India being a country under the law of which the registration referred to is in fact in force; or
(b) where that other expression is of itself such as to indicate that the reference is to such registration as is mentioned in clause (a); or
(c) where that word is used in relation to a layout-design registered as a layout-design under the law of a country outside India and in relation solely to such layout-design.
Section 57, The Semiconductor Integrated Circuits Layout-Design Act, 2000 (Act 37 of 2000).
Cross-references
Extracted from the operative text of the enactments themselves. Every destination below exists in our corpus.
Referred to by 1
Questions about Section 57
What does Section 57 of the Semiconductor Integrated Circuits Layout-Design Act deal with?
Section 57 of the Semiconductor Integrated Circuits Layout-Design Act is headed "Penalty for falsely representing a layout-design as registered". No person shall make any representation with respect to a layout-design not being a registered layout-design, to the effect that it is a registered layout-design.
How do I find court cases under Section 57 of the Semiconductor Integrated Circuits Layout-Design Act?
In judgments and charge sheets this section is written several ways, and each form finds a different set of orders. These search the full text of every order eCourtsIndia holds, best matches first: Semiconductor Integrated Circuits Layout-Design Act 57, section 57 Semiconductor Integrated Circuits Layout-Design Act, section 57 of the Semiconductor Integrated Circuits Layout-Design Act. Each opens the full list of orders on eCourtsIndia, where it can be narrowed by court, year and outcome.
What should I read with Section 57 of the Semiconductor Integrated Circuits Layout-Design Act, and has it changed?
1 other provision in this corpus refers back to it.
When did Section 57 of the Semiconductor Integrated Circuits Layout-Design Act come into force?
Section 57 of the Semiconductor Integrated Circuits Layout-Design Act, cited as Semiconductor Integrated Circuits Layout-Design Act 57, came into force on 01 May 2004, having been enacted on 04 Sep 2000. It is in force as at the date shown on this page.
Other sections of this Act
Source and method. Compiled from the enactments of Parliament and of the State legislatures as published on India Code, and republished together with commentary and other original matter under section 52(1)(q)(ii) of the Copyright Act, 1957. Structured, cross-referenced and maintained by eCourtsIndia. Text as in force on 17 Oct 2026. This page is not a substitute for legal advice.